1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory device in which a memory cell has a capacitor. More specifically, the present invention relates to a method of driving sense amplifiers provided in a dynamic semiconductor memory device for sensing and amplifying memory cell data.
2. Description of the Background Art
FIG. 30 schematically shows a structure of a main portion of a dynamic semiconductor memory device in the prior art. In FIG. 30, a memory cell MC is arranged corresponding to a crossing between a word line WL extending in a row direction and a bit line pair BLP extending in a column direction. Each word line WL is connected to memory cells arranged in one row. Each bit line pair BLP including bit lines BL and /BL is connected to memory cells arranged in one column. FIG. 30 representatively shows memory cell MC arranged on the crossing between word line WL and bit line BL. Memory cell MC includes a memory cell capacitor MQ for storing information in the form of electric charges, and an access transistor MT formed of an n-channel MOS transistor for connecting memory cell capacitor MQ to bit line BL in response to a voltage on word line WL. The memory cell is not arranged on the crossing between word line WL and complementary bit line /BL paired with bit line BL.
For bit line pair BLP, a bit line precharge/equalize circuit P/E which precharges and equalizes bit lines BL and /BL to a predetermined precharge voltage VBL in response to activation of an equalize instructing signal .phi.EQ, a sense amplifier SA which is activated in response to activation of sense drive signals .phi.SDP and .phi.SDN, to differentially amplify voltages on bit lines BL and /BL, and a column select gate CSG which connects bit line pair BLP to an internal data line pair IOP in response to a column select signal Y are further provided. Column select gate CSG includes transfer gates provided corresponding to bit lines BL and /BL, respectively.
Sense amplifier SA includes cross-coupled p-channel MOS transistors as well as cross-coupled n-channel MOS transistors. Operation will now be briefly described.
In a standby cycle, word line WL is at a ground voltage level, and access transistor MT in memory cell MC is off. Sense amplifier SA is inactive, and column select gate CSG is off. Equalize instructing signal .phi.EQ is active so that bit line precharge/equalize circuit P/E is active to hold bit lines BL and /BL at predetermined voltage VBL level.
When a memory cycle starts, equalize instructing signal .phi.EQ becomes inactive, and bit line precharge/equalize circuit P/E stops the operation of precharging and equalizing the bit lines. Bit lines BL and /BL are in a floating state at precharge voltage VBL level.
A row selecting operation is performed so that word line WL is driven to the selected state in accordance with an address signal, and a voltage level on word line WL rises. Responsively, access transistor MT is turned on so that memory cell capacitor MQ is electrically connected to bit line BL, and charges move between bit line BL and memory cell capacitor MQ. When data stored in memory cell MC is at H-level, the voltage level on bit line BL rises. When data stored in memory cell MC is at L-level, the voltage level on bit line BL lowers. Complementary bit line /BL holds the voltage level of precharged voltage VBL.
When the voltage difference between bit lines BL and /BL is adequately developed, sense drive signals .phi.SDP and .phi.SDN are driven to the active state, and sense amplifier SA differentially amplifies and latches the voltages on bit lines BL and /BL.
Then, column selection is performed. In this operation, column select signal Y is driven to the selected state in accordance with an address signal so that column select gate CSG is turned on to connect bit line pair BLP to internal data line pair IOP. Then, data is read from or written into memory cell MC.
In the dynamic semiconductor memory device, each memory cell MC is formed of one capacitor and one transistor, and therefore occupies a small area. Thus, the memory cell has a structure suitable to high-density integration, and dynamic semiconductor memory devices such as a DRAM (Dynamic Random Access Memory) have been widely used as semiconductor memory devices of large storage capacities.
With increase in integration density of the semiconductor memory device, sizes of elements are reduced. A power supply voltage must be lowered for ensuring breakdown characteristics of gate insulating films and others of components, i.e., MOS transistors (insulated gate field-effect transistors) having such reduced sizes. Reduction in element size is performed according to a predetermined scaling rule. In the MOS transistor, however, it is generally difficult to lower the threshold voltage in accordance with the power supply voltage which in turn is lowered in accordance with the predetermined scaling rule. This is due to the following fact. Even if MOS transistor has a gate-source voltage Vgs set at 0 V, a leakage current (sub-threshold current) flowing therethrough would increase with decrease in absolute value of the threshold voltage, and this leakage current would not be negligible. Accordingly, the absolute value of the threshold voltage is set to a predetermined value sufficiently reducing the sub-threshold leakage current.
FIG. 31 shows a structure of sense amplifier SA. In FIG. 31, sense amplifier SA includes a p-channel MOS transistor PT1 which is connected between a sense drive signal line SDP and bit line BL and has a gate connected to bit line /BL, a p-channel MOS transistor PT2 which is connected between sense drive signal line SDP and bit line /BL and has a gate connected to bit line BL, an n-channel MOS transistor NT1 which is connected between a sense drive signal line SDN and bit line BL and has a gate connected to bit line /BL, and an n-channel MOS transistor NT2 which is connected between sense drive signal line SDN and bit line /BL and has a gate connected to bit line BL.
Sense drive signal line SDP transmits sense drive signal .phi.SDP, and sense drive signal line SDN transmits sense drive signal .phi.SDN. Sense drive signal .phi.SDP has an amplitude between VBL and Vcc, and sense drive signal .phi.SDN has an amplitude between VBL and Vss. When sense drive signal .phi.SDP is active (at power supply voltage Vcc level), p-channel MOS transistors PT1 and PT2 drive one of bit lines BL and /BL at a higher potential to power supply voltage Vcc level. When sense drive signal .phi.SDN is active (at ground voltage Vss level), n-channel MOS transistors NT1 and NT2 drive the other bit line BL or /BL at the lower potential to ground voltage Vss level.
In a general sense operation, sense drive signal .phi.SDN is first activated, and then sense drive signal .phi.SDP is activated. When bit lines BL and /BL have been precharged to the voltage level of intermediate voltage VBL (=Vcc/2), the gate-source voltages of n-channel MOS transistors NT1 and NT2 take (.DELTA.V+Vcc/2) as the maximum value, where .DELTA.V represents a read voltage read onto the bit line. When the voltage level of power supply voltage Vcc lowers, the gate-source voltages of n-channel MOS transistors NT1 and NT2 lower, and the driving power lowers because the current driving power of the MOS transistor depends on the gate-source voltage. Consequently, the fast sense operation cannot be implemented. Likewise, a drain-source voltage Vds lowers, and a drain current decreases so that fast charging/discharging (sensing) cannot be implemented.
Likewise, p-channel MOS transistors PT1 and PT2 amplify the bit line voltage difference enlarged by the above sense operation of n-channel MOS transistors NT1 and NT2. However, when power supply voltage Vcc is low, the maximum value Vcc of the gate-source voltages of p-channel MOS transistors PT1 and PT2 is low so that fast sensing (restoring) cannot be done.
In 64-Mbit DRAMs in the present generation, one bit line pair is connected to the memory cells of 126 bits. In DRAMs in the next generation, 256 memory cells are connected to one bit line, and the bit line capacitance increases. Accordingly, the bit line load cannot be driven fast under the low power supply voltage condition, and therefore fast access cannot be achieved.
Various structures have been proposed for implementing fast sensing with the low power supply voltage.
FIG. 32A schematically shows a structure of a sense drive control circuit in the prior art. In FIG. 32A, bit lines BL and /BL are divided into cell bit lines BLC and /BLC and sense bit lines BLS and /BLS with a bit line isolating gate BIG. Memory cell MC is connected to cell bit lines BLC and /BLC. Sense amplifier SA is connected to sense bit lines BLS and /BLS. Bit line isolating gate BIG is supplied with a bit line isolation control signal /.phi.BI via an inverter IV1.
Sense amplifier SA includes cross-coupled p-channel MOS transistors PT1 and PT2 as well as cross-coupled n-channel MOS transistors NT1 and NT2, similarly to the structure shown in FIG. 31. A sense drive line SALa is connected to a source node SPL of sense amplifier SA, and a sense drive line SALb is connected to a source node SNL of sense amplifier SA.
Sense drive line SALa includes a boost capacitance Csp which receives a boost control signal fBSP on one electrode thereof, an n-channel MOS transistor PR3 which is turned on to transmit intermediate voltage Vcc/2 when sense activating signal /.phi.LP is inactive, and a p-channel MOS transistor PR3 which is turned on to transmit power supply voltage Vcc when sense activating signal /.phi.LP is active. Sense drive line SALb is connected to a boost capacitance Csn which receives a boost control signal .phi.BSN on one electrode thereof, an n-channel MOS transistor NR4 which is turned on to transmit intermediate voltage Vcc/2 when sense activating signal /.phi.LN is inactive, and an n-channel MOS transistor NR5 which receives sense activating signal /.phi.LN on a gate thereof via an inverter IV2 and is turned on to transmit ground voltage Vss when sense activating signal /.phi.LN is active (L-level). Operation of the sense drive control circuit shown in FIG. 32A will now be described with reference to a signal waveform diagram of FIG. 32B.
In a standby cycle, isolation control signal /.phi.BI is at L-level, the output signal of inverter IV1 is at H-level, and bit line isolating gate BIG is on. Therefore, cell bit lines BLC and /BLC are connected to sense bit lines BLS and /BLS, respectively. Boost control signal .phi.BSP is at the ground voltage level, and boost control signal .phi.BSN is at power supply voltage Vcc level. Sense drive lines SALa and SALb are already precharged to the voltage level of intermediate voltage of Vcc/2 by MOS transistors NR3 and NR4. Likewise, bit lines BL and /BL are already precharged to the voltage level of intermediate voltage of Vcc/2 by the bit line precharge/equalize circuit (see FIG. 30).
When a memory cycle starts, word line WL is first driven to the selected state in accordance with a row address signal. As the voltage on word line WL rises, data stored in memory cell MC is transmitted onto bit lines BLC and BLS (FIG. 32B shows the signal waveforms in the operation of reading data at H-level). Since bit lines /BLC and /BLS are not connected to the memory cell, they maintain the level of intermediate voltage of Vcc/2.
When the voltage difference between sense bit lines BLS and /BLS increases, bit line isolation control signal /.phi.BI attains H-level at a predetermined timing, bit line isolating gate BIG is turned off, and sense bit lines BLS and /BLS are isolated from cell bit lines BLC and /BLC, respectively. The memory cell is not connected to sense bit lines BLS and /BLS, and the load driven by sense amplifier SA is sufficiently small. At substantially the same time as turn-off of bit line isolating gate BIG, sense activating signals /.phi.LN and /.phi.LP are driven to the active state at Llevel. Thereby, MOS transistors NR3 and NR4 are turned off, and MOS transistors PR3 and NR5 are turned on.
Sense drive line SALb is supplied with ground voltage Vss, and MOS transistors NT1 and NT2 discharge one (/BLS) of sense bit lines BLS and /BLS at a lower potential to the ground voltage level. Sense drive line SALa is supplied with power supply voltage Vcc, and MOS transistors PT1 and PT2 drive sense bit line BLS to the level of power supply voltage Vcc. During the sense operation of sense amplifier SA, only sense bit lines BLS and /BLS are driven. Therefore, the load driven by the sense amplifier SA is merely formed of parasitic capacitances of sense bit lines BLS and /BLS as well as parasitic capacitances such as junction capacitances of MOS transistors NT1, NT2, PT1 and PT2. Accordingly, the load is sufficiently small, and the sense operation can be performed fast even if the voltage level of power supply voltage Vcc is low.
After sense amplifier SA completes the sense operation, isolation control signal /.phi.BI is driven to L-level at a predetermined timing, and bit line isolating gate BIG is turned on to connect bit lines BLC and BLS and to connect complementary bit lines /BLC and /BLS. At this time, boost control signal .phi.BSP is driven from the ground voltage level to the power supply voltage level, and boost control signal .phi.BSN is driven from the power supply voltage level to the ground voltage level. That is, sense drive lines SALa and SALb are overdriven, the voltage level on sense drive line SALa exceeds power supply voltage Vcc, and the voltage level on sense drive line SALb becomes lower than ground voltage Vss. By overdriving sense drive lines SALa and SALb, electric charges can be fast supplied to suppress variations in voltage level on sense bit lines BLS and /BLS even in the case where the variation in voltage level may occur on sense bit lines BLS and /BLS due to connection of sense bit lines BLS and /BLS to cell bit lines BLC and /BLC, respectively. Thereby, restoring of data into memory cell MC can be precisely and reliably performed.
After completion of the restoring, access to a memory cell (column selection) is performed, and data is written or read.
According to the method of isolating the sense amplifier and overdriving the sense drive lines as shown in FIG. 32A, it is necessary to determine accurately the timing for turning off bit line isolating gate BIG and starting the sense operation. If bit line isolating gate BIG were turned off at a fast timing for implementing fast sense operation, an adequate voltage difference would not occur between sense bit lines BLS and /BLS, and accurate sensing would be impossible. If bit line isolating gate BIG were turned off after start of the sense operation, the load to be driven by sense amplifier SA would be large, and therefore fast sensing would be impossible. As the simplest approach, the sensing start timing (i.e., timing for activating sense activating signal /.phi.LN) may be set the same as the timing for turning off bit line isolating gate BIG. Even in this case, however, bit line isolating gate BIG and sense amplifier SA are driven by different control signals, and an appropriate timing margin is required for activating sense amplifier SA under a low load. Accordingly, timing control is difficult, and it is difficult to perform sense operation at high speed.
Further, restoring is required after the sensing, and the period for the restoring increases the time period of the memory cycle, which also impedes fast access.